Traffic actuated control system



March 24, 1970 c. L. Du VIVIER TRAFFIC ACTUATED CONTROL SYSTEM '7Sheets-Sheet l Filed June 2, 1967 6511. VIE@ 2022 m m V m CHARLES L.DUV|V|ER ATTORNEY March 24, 1970 c. l.. Du VIVIER TRAFFIC ACTUATEDCONTROL SYSTEM 7 Sheets-Sheet 2 Filed June 2. 196'? ATTORNEY March 24,1970 c. l.. DU vlvu-:R

TRAFFIC ACTUATED CONTROL SYSTEM '7 Sheets-Sheet File-: June 2, 1967March 24, 1970 Filed June 2, 1967 C. L. DU VIVIER TRAFFIC ACTUATEDCONTROL SYSTEM 7 Sheets-Sheet 4 RED. RETURN z No CALL |543 CALL-AWAY oNEADVANCE HOLD SHOT j SEMI-CALI.

A78 E MAXTIMER 1sT L! sEMl- CALL T z VEHICLE T|MER @'9| |38 J|92 (5) (l)tg ,|40 '4| 42 x lNTERvAL TIMES l l lM7 DC TR ST DMV (5) SEMI- CALL-330 (2) N56 sToP T|M|NC lNTERvAL l -TIMER ADVANCE RESET HOLD Go To PREP.

sEM|CALL CALL-AWAY M64 i No CALL gAxTjMm EsET (2) i 23 FIG. 5 4 TR AADVANCE 334 INVENTOR sEM|-CA| L. r CHARLES L. DuvlvlER sToP TIMING BY V@AMK/g ATTORNEY March 24, 1970 C, Du VIVIER 3,503,041

TRAFFIC AOTUATED CONTROL SYSTEM Filed June 2. 1967 '7 Sheets-Sheet 5[|98 I94\ IMP (5) M coNv f204 l :GAP RESET 206 i208 f2|9 [220 STOPTIMING ST s' I 50 FF LVP I NO CALL `2I8 CALL AWAY L 205 2|7 HOLD IMP III`22| I GAP REDUCTION TIMER CONV FIG. 6

(232 234 236 I PASSAGE TIMER ST VEHICLE WAITING FIG. 7

Bx Ext HOLD 598 I al HOLD INVENTOR.

CHARLES L. DUVIVIER March 24, 1970 c. l.. DU vlvn-:R

TRAFFIC ACTUATED CONTROL SYSTEM Filed June 2. 1967 March 24, 1970 c. L.Du vlvlER 3,503,041

TRAFFIC AGTUATED CONTROL SYSTEM Filed June 2, 1967 '7 Sheets--Shee'cI '7AIPNFFI BIPNFFI INVEN TOR.

A3 PNFFI Y CHARLES L DuvlvlER BBPNFFI `540 FSG. IO cwozffaw ATTORNEYUnited States Patent O U.S. Cl. 340--37 11 Claims ABSTRACT OF THEDISCLOSURE A solid-state traffic actuated multi-phase intersectionright-of-way control system capable of providing right-ofway to up totwo of a plurality of non-confiicting traffic phases selected from alarger plurality of trafiic phases at an intersection. Gating andcontrol circuitry selects the traffic phases to which right-of-way is tobe assigned, insuring that right-of-way is not simultaneously assignedto conliicting trafiic phases. Timing and counter circuitry steps eachright-of-way period through its appropriate intervals. The right-of-wayassignment can be changed from first and second non-confiicting trafficphases to third and fourth non-conflicting traffic phases, and one ofthe third and fourth phases may be the same as one of the first andsecond phases.

BACKGROUND OF THE INVENTION This invention relates to a traffic actuatedmultiphase trafiic intersection right-of-way control system. Moreparticularly this invention relates to such a traic intersectionright-of-way control system including all solid state circuitry inmodular components and having the ability to assign right-of-way to oneor more non-conflicting phases of a plurality of traf-lic phases at inintersection in accordance with the demand on any one phase relative tothe overall demand on all trafiic phases.

While many trafiic intersections are primarily utilized by trafiicflowing straight through on one thoroughfare or straight through on theother intersecting thoroughfare, numerous intersections handle largequantities of traffic desiring to turn left from one thoroughfare,across the traffic lanes assigned for traic fiow in the oppositedirection on that first thoroughfare, and into the second thoroughfare.So long as this left-turn trafiic is of a small volume it presents nogreat problem. However, when the volume of left-turn traffic increasesappreciably, it becomes desirable to assign portions of the right-of-wayperiod exclusively for the left-turn trafiic. For example, at anintersection of a north-south street and an east-west sreet, sometrafiic traveling in a northerly direction may desire to turn left ontothe east-west street to then travel in a westerly direction. To bestaccommodate large volurnes of this left turn traffic it is necessary toend the rightof-way period of the south-bound trafiic so that theleftturn traffic may pass in front of it.

If there is south-bound trafiic desiring to turn left into theeast-bound lane, then, these two left-turn flows can take placesimultaneously. This necessitates stopping the straight throughnorth-bound tratiic. lf, however, there is no left-turn trafiic in thesouth-bound lanes, then the north-bound left-turn traffic can proceedsimultaneously with the north-bound straight through traffic. Thus, thenorth-bound left-turn trafiic can proceed simultaneously either with thesouth-bound left-turn trafiic or with the north-bound straight throughtrafiic. Similarly, the southbound left-turn trafiic can proceedsimultaneously either with the north-bound left-turn traffic or thesouth-bound straight through trafiic, and the north-bound straightthrough traffic and south-bound straight through trafiic 3,503,041Patented Mar. 24, 1970 ice each can proceed simultaneously with theircorresponding left-turn traffic or simultaneously with each other.Left-turn east-bound and west-bound trafiic similarly each have twotrafiic fiows with which they can proceed. Thus, it is seen that at suchan intersection any one trafiic fiow can safely take place at the sametime as either one of two selected other traf-'ric fiows. Optimumassignment of right-of-way between the conflicting phases of the traicflow requires that any one phase be permitted to operate simultaneouslywith either one of its non-conflicting phases which has a demand forright-of-way.

Traffic control systems are available for providing right-of-way to eachof two mutually confficting trafiic phases at an intersection. Use ofsuch a control system at an intersection having large amounts ofconflicting straight through and left-turn traffic results in theleft-turn traffic encountering a great deal of difficulty. Not only doesthis result in only a few left-turn vehicles passing during each cycleof the control system, but also it presents a hazard because morevehicles attempt to turn left than can, with a resulting conflictbetween these left-turn vehicles and vehicles attempting to travelstraight through on the subsequent phase. Left-turn traffic at atwo-street intersection can be accommodated by use of a three-phase or afourphase trafiic controller. Then, one phase is assigned exclusivelyfor left-turn traffic in a three-phase controller or two phases of afour-phase controller are assigned for the two left-turn movements, i.e.one left-turn movement by the north-south traffic and another left-turnmovement by the east and west bound traffic. The controller then cyclesthrough its phases to periodically allocate right-ofway to thisleft-turn traffic. While this smoothes the traffic flow somewhat, itdoes not make optimum utilization of trafiic control equipment and itneedlessly holds up one direction of straight through traffic when thereis no trafiic turning left across its pathway until the left-turntraffic originating from the same direction as that straight throughtraic has terminated. Thus, optimum trafiic handling is not obtained.

Leftturn trafiic can also be accommodated by adding to a control systemone or more small control units, frequently referred to as minormovement controllers, which interrupt the normal trafiic signal cyclesequence to provide left-turn indications prior to the straight throughindications. By use of one such minor movement controller for eachdirection of left-turn trafiic, improved traffic flow can be obtained.However, the leftturn indication can only be provided at one selectedpoint in the trafiic controller cycle. Thus, if at the time that pointis reached there is no demand for the left-turn indication, then theleft-turn is omitted, and the straight through indications are provided.If, shortly after the initiation of a straight through indication ademand for a left turn originates on that phase, that demand must remainunsatisfied until the selected point in the cycle is again reached. Ifthere is no demand on the intersecting roadway, either right-of-way muststill be transferred to that roadway in order to cycle through to thepoint at which the minor movement controller can allow left-turn trafficto have the right-of-way, or further control equipment must be added toenable the system to skip the phase having no demand. Thus, obtainingoptimum trafiic control with such a system requires numerous complexieces of control equipment, thereby increasing the likelihood of anequipment malfunction.

Trafiic control systems have been developed which are of unitary designand which are able to improve trafiic flow by omitting one or morephases of a traffic controller cycle in order to provide a left-turnindication when demanded on a street which has right-of-way, in theabsence of a call for the traffic right-of-way from a conflicting phase.These traffic control systems heretofore have been large units utilizingvacuum tubes, relays, cams, and other electro-mechanical devices Notonly do such systems consume large amounts of power, they also aresubject to frequent breakdown due to the nature lof theelectro-mechanical devices.

In addition, prior art traffic control systems of this type have beenincapable of adequately handling traffic approaching the intersection inwaves or platoons. Consider, for example, an intersection of twostreets, at least one of which has a high volume of left-turn traliicfor which a separate tratiic phase is assigned. Each rightof-way periodcomprises several intervals. There will be an initial green interval,which may coincide with pedestrian walk and pedestrian clearanceintervals if these are provided. Then there isa vehicle or passageinterval during which right-of-way is continued on that traffic phase solong as the traffic volume on that phase justifies. This is followed bya brief interval, frequently known as a preparatory interval, duringwhich the control system determines the phase to which right-of-way isto be transfered next. Then comes the yellow or clearance interval andperhaps an all-red interval for the traffic phase, following whichright-of-way is transferred to another phase. If right-of-way at anintersection is assigned to a straight through traliic phase, forexample east-bound straight through, and to the non-conflictingleft-turn traic phase (i.e. east-bound left-turn becoming northbound)when a call for right-of-way is received from the opposite non-conictingstraight through phase, (i.e., west-bound straight-through) followed bya call for rightof-way from a conflicting traic phase, for example,northbound, prior art traic control systems of this type have permittedthe east-bound straight through phase circuitry to advance to itspreparatory interval regardless of the status of the west-bound straightthrough right-of-way period, provided the straight-through traffic onthe eastbound phase at some time reaches a low volume. But right-of-wayis not transferred to the coniiicting northbound phase until thewest-bound straight-through phase has passed through its vehicleinterval to its preparatory interval. During the time the west-boundphase is in its initial interval, the east-bound trahie volume mayincrease considerably due to the arrival of another wave or platoon oftraflic at the itnersection. However, in prior art traitic controlsystems of this type, the east-bound phase circuitry is held in itspreparatory condition. Thus, if the West-bound traflic volume drops,right-of-way transfers to the conicting north-bound phase, cutting olfthe east-bound platoon which is at the intersection. As a consequence,optimum trathc iiow is not achieved.

SUMMARY OF THE INVENTION The present invention is a trahie-actuatedmulti-phase traic intersection right-of-way control system in whichduring the time right-of-way is assigned to one traic phase,right-of-way can also be assigned to any one of a plurality ofnon-conicting traic phases selected from a larger plurality of traicphases at the intersection. The control system can change theright-of-way assignment from one of the non-conicting traflic phases toanother non-coniiicting phase, while retaining right-of-way on thesecond non-conflicting traflic phase, as traflic demands require and inthe absence of a call for right-of-Way on the conflicting trafficphases. In the event that right-of-way is given to a straight throughtraflic phase simultaneously with its non-conflicting left-turn trafficphase, and a call comes in for the non-coniiicting straight throughright-ofway followed by a call for right-of-way on a conicting traticphase, the first straight through traffic right-of-way is maintained inits vehicle interval at least until the rightof-way period has beenassigned to the other straight through traic and has reached its vehicleinterval. Thus, a platoon of traiiic arriving on the rst straightthrough phase while the seven@ straight through phase is in its initialinterval is optimally handled. The traffic control system is made upentirely of solid state circuitry, with no vacuum tubes or moving parts,and it is adapted for simpliiied modulator construction, thus permittingeasy expansion of the system to meet the growing requirements of anintersection.

It is accordingly an object of the present invention to provide animproved traic actuated multi-phase trallic intersection right-of-waycontrol system.

It is another object of the present invention to provide an improvedtrahie-actuated multi-phase intersection controller having a simpliedsolid state design resulting in improved performance and reliability.

It is a further object of the present invention to provide a trafficcontroller which permits optimum assignment of right-of-way atintersections having complex traliic requirements.

It is yet another object of the present invention to provide a traiiicintersection right-of-way controller which, during the time thatright-of-way is available to any one traic phase, can assignright-of-way simultaneously to any one of a plurality of non-conflictingtraffic phases and which in response to a demand therefor can changethat assignment to lany other non-conicting trafc phase in the absenceof a call for right-of-way from a conflicting traffic phase.

It is a still further object of the present invention to provide atraffic intersection right-of-way control system capable ofsimultaneously allocating right-of-way periods, each having a pluralityof intervals, to first and second non-contlicting traffic phases at anintersection and, when a call for right-of-way is received from a thirdtrahie phase conflicting with the second phase but not with the rst,capable of holding the right-of-way period of the lirst phase in auintermediate interval from which it can not be removed in the presenceof continuing traic demand even in the presence of a call forright-of-way from a fourth phase, conflicting with the first threephases, where the fourth phase call arrives after the third phase call,the irst phase right-of-way being held in that intermediate interval atleast until the third phase has received right-ofway and has reached thecorresponding intermediate interval.

These and other objects and advantages of the present invention will beapparent from the following detailed description and claims,particularly when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a streetintersection at which the right-of-way is controlled -by the traflicactuated multiphase control system of the present invention.

FlG. 2 is a block diagram of the traffic actuated multiphase trafliccontrol system of the present invention.

FIG. 3 is a detailed block diagram of the counter circuitry within theinterval sequence units used in the present invention.

FIG. 4 is a detailed block diagram of a phase control unit for use inthe present invention in connection with any of the traic phases.

FIG. 5 is a detailed block diagram of the gating and timing circuitrywithin an interval sequence unit as used in the present invention.

FIG. 6 is a detailed block diagram of gap timing circuitry within theinterval sequence units used in the present invention.

FIG. 7 is a detailed block diagram of a passage timing circuit withinthe interval sequence units used in the present invention.

YFIG. 8 is a block diagram of the phase sequence unit of the presentinvention showing in detailed block form the portion of the phasesequence unit which works in common with all traliic phases at theintersection.

FIG, 9 is a block diagram depicting one Strt of phase selectioncircuitry within the phase sequence unit used in the present invention.

FIG. is a detailed block diagram of the transfer gating circuitry withinthe phase sequence unit used in the present invention.

FIG. 11 is a detailed block diagram of a set of hold gating circuitryutilized to coordinate operation of the system and found within thephase sequence unit used in the present invention.

DESCRIPTION OF A PREFERRED EMBODIMENT FIG. l depicts a streetintersection which may be controlled by means of a multi-phase trafiicactuated intersection control system incorporating the presentinvention. The intersection depicted in FIG. 1 includes two streets,each having two lanes of travel in each of two directions, the two lanesof travel being divided by a median or divider strip. There is providedin each direction of travel for a brief distance approaching theintersection an additional lane for the convenience of vehicles desiringto make a left turn into the cross street. The east-West street isdesignated street I, while the north-south street is designated streetII. There are thus eight phases of tratiic approaching the intersection:phase A1, the straight through west-bound traic; phase A2, the straightthrough eastbound traic; phase A3, the straight through south-boundtraiiic; and phase A4, the straight through north-bound traic; phase B1,the east-bound left-turn traic becoming north-bound; phase B2, thewest-bound left-turn traffic `becoming south-bound; phase B3, thenorth-bound leftturn tral'lic becoming west-bound; and phase B4, thesouth-bound left-turn traic becoming east-bound. These designations areof course only for convenience and are in no way limiting. By means ofthese designations it is seen that each straight through traic phase isdesignated as an A phase while each left-tum tratlic phase is designatedas a B phase. In addition, it can be seen from FIG.

1 that each odd traic phase conilicts with all other odd traflic phasesand that each even traic phase conicts with all other even traic phases.In addition, there are conicts between certain odd-even pairs of traflicphases such as phases B1 and B4, phases B1 and A4, and phases A2 and A3,for example. The pairs of non-conflicting traic phases which can operatesimultaneously at the illustrative intersection depicted in FIG. 1 arethus the following: phases A1 and A2, phases -A1 and B2, phases A3 andA4, phases A3 and B4, phases B1 and A2, phases B1 and B2, phases B3 andA4, and phases B3 and B4. Each of these pairs is seen to include one oddphase and one even phase due to the designations used in thisillustrative example.

Vehicles on each traicphase approaching the intersection are monitoredby a vehicle detector, depicted in FIG. 1 by the vehicle detector blocksD shown in the roadway approaching the intersection for each traicphase. Thus, for example, vehicles on phase A1 are monitored by detectorDA1, vehicles on phase B3 are monitored by vehicle detector DB3, etc.Each of these vehicle detectors may be any one of a number of types. Forexample, each m-ay be an overhead detector of a radar or sonic type.Alternatively each may be imbedded in the roadway, in which case theymay be inductive loop, magnetic, or treadle detectors, for example. Itis required only that each detector generate an electrical signal uponthe passage of a vehicle in its detection zone, although a detectorproviding an electrical signal in response to the presence of a vehiclemay be used, if desired.

Manually actuated push-buttons are provided at the corners of theintersection, to be actuated by pedestrians desiring to cross theintersection. These pedestrian pushbuttons are shown in each corner ofthe intersection by the outlines P, and they are designated inaccordance with the vehicle phase with which they cooperate. Thus, apushbutton PA1 is utilized by pedestrians wishing to cross theintersection in -a direction parallel with vehicle phase A1, etc.Pedestrians desiring to cross the intersection push the appropriatepedestrian button to actuate circuitry in the invention which results insignalling of a pedestrian rightof-way interval.

Tralic control signals to control right-of-way phases for each traicph-ase and for each pedestrian phase are provided at the intersection.For clarity these traffic control signals are collectively depicted inFIG. l by the circle S at the center of the intersection; however, theymight conveniently be located directly in front of the traffic lanescorresponding to each phase and directly facing pedestrians desiring tocross the intersection.

Each of the vehicle detectors D and pedestrian pushbuttons P and thetraffic control signal S is connected by means of cabling (not shown) toa terminal box TB illustratively shown in one corner of theintersection. Such a terminal box housing the necessary circuitry forthe present invention might be placed lat any convenient location at ornear the intersection or might be placed at a remote location.

FIG. 2 depicts the multi-phase traic actuated intersection controlsystem of the present invention in block diagram form. A phase controlunit is associated with each tralc phase at the intersection. Thus,phase control unit 10 is associated with the traic phase A1, phasecontrol unit I12 is associated with traffic phase A3, phase control unit14 is associated with traffic phase B1, phase control nnit 16 isassociated with tr'aic phase B3, phase control unit 18 is associatedwith traiilc phase A2, phase control unit 20 is associated with traflicphase A4, phase control unit 22 is associated with traic phase B2, andphase control unit 24 is associated with traic phase B4.

Each phase control unit receives indications from its associated vehicledetector and pedestrian push-buttons and transmits signals to theassociated vehicle and pedestrian signal lights. Phase control unit 10associated with traflic phase A1 is typical of the phase control unitswhich are associated with the four phase A traic phases. Phase controlunit 10 receives vehicle detection signals from the vehicle detector DA1and receives pedestrian call signals from the pedestrian push-buttonsPA1. Phase control unit 10 provides appropriate outputs for control ofthe vehicle and pedestrian signal lights of phase A1 for control ofright-of-way and clearance. Each of the other phase A control units 12for A3, 18 for A2, and 20 for A4 is similar to phase control unit 10,but has inputs from the vehicle detector and pedestrian pushbutton ofthe associated phase and has outputs for the traffic control signals forsuch phase.

Phase control unit 14, assoicated with traic phase B1, is typical of thephase lcontrol units which are associated with the four -B trafficphases. Control unit '14 receives v vehicle detection indications fromvehicle detector DB1 and provides control outputs to vehicle traflicsignals associated with phase B1. Phase control units 16, 22, and 24associated respectively with traflic phases B3, B2, and B4 similarlyreceive vehicle indications from the vehicle detectors DB3, DB2, and DB4associated with their respective traffic phases and provide vehiclecontrol signals to the associated traic signals. Since the B traicphases are left-turn phases at the intersection of FIG. 1, no pedestrianactuations or pedestrian control signals are associated with the phasecontrol units at phase B.

Each of the phase control units 10, 12, 14, 16, associated with the oddtraiiic phases, is connected to interval sequence unit 26 whichdetermines the sequence of intervals for the control periods of the oddtraffic phases. These odd phase control units both receive signals frominterval sequence unit 26 and apply signals to interval sequence unit26. Similarly, each of the phase control units 18, 20, 22, 24, isconnected to interval sequence unit 28 which determines the sequence ofintervals for the control periods of the even traliic phases. Each evenphase control unit 18, 20, 22, 24 both receives signals from intervalsequence unit 28 and applies signals to interval sequence unit 28.

Each of the phase control units 1024 and each of the interval sequenceunits 26 'and 28 is connected to phase sequence unit 30 to both receivesignals therefrom and apply signals thereto. Phase sequence unit 30determines which phase control units shall provide right-of-wayindications at any one time and which phase control units shall be nextto supply right-of-way indications, insuring that no conflictingright-of-way indications are provided. At any one time one of the oddphase control units 10, 1.2, 14, 16 may be selected by phase sequenceunit 30 to provide control indications to its associated trathc phaseand a non-conflicting one of the phase control units 18, 20, 21, 24 maybe simultaneously selected to provide control indications to itsassociated traffic phase.

The phase control units selected by phase sequence unit 30 from thephase control units 10424 provide ap propriate control indications fortheir associated trafc phases and develop voltage analogs of thedurations of each interval of the control sequence. Interval sequenceunit 26 monitors these analog timing signals for the selected oddtraliie phase, and in response to these monitored signals, the intervalsequence unit 26 provides indications for a sequence of steps andappropriate intervals for the control period of that selected odd phasecontrol unit. Similarly, interval sequence unit 28 monitors the analogtiming signals for the selected even trafc phase control unit andprovides indications for a sequence of steps and a-ppropriate intervalsfor the control period for that selected even phase.

INTERVAL COUNTER-FIGURE 3 FIG. 3 depicts a nine position counter, one ofwhich is used in each interval sequence unit. The counter cornprises twothree-position units 52 and 54. Each of these units comprises a trinarycounter, and the two units are connected to obtain nine discrete countpositions. A trinary counter suitable for this use is disclosed in U.S.Patent No. 3,267,424 granted to Peter C. Brockett and Charles L.DuVivier on Aug. 16, 1966, particularly in conjunction with components356 and 356 in FIGURE 5 of that of that patent. The outputs of the threestages of each of the counter units 52 and 54 are coupled to AND gates56-72 in such a manner that the outputs of the gates 56-72 correspondrespectively with the positions 1-9 of the counter output. Pulsesapplied to the stepping input of counter unit 52 via line 74sequentially step the counter through its nine positions. Thus, if thecounter is in its position 1 so that signals are applied to the twoinputs of AND gate 56, then gate 56 provides an output signal.Application of a pulse on line 74 steps the counter to its position 2,resulting in termination of the signal applied from counter unit S2 toAND gate S6 and application of signals to the two inputs of AND gate 58.Thus, the position 1 output from gate 56 ends and a position 2 outputsignal is provided from gate 58. The next pulse on line 74 steps thecounter to its position 3, thereby terminating the output from gate 58and initiating an input from AND gate 60. Under some conditions theadvance pulse is blocked from line 74 and instead sets the counter toanother position which skips one or more intermediate positions, asexplainedl more fully hereinafter. When the counter is in its position9, a pulse on line 74 returns it to position 1, returning the position 1output signal from gate 56.

The counter position outputs 1-9 obtained from gates 56-72 respectivelyas the nine position counter moves through its positions correspond tointervals in the control period. Thus the rst counter position, in whichan output is obtained from gate 56, corresponds to the first interval ofthe control period known as the green skip interval. This is a shortduration interval providing a green or go indication to vehicular traicwhile maintaining a. dont walk or wait indication for pedestrians.Should it be desired to provide sub-cycles by use of auxiliary controlequipment, these sub-cycles can be operated while the counter is in itsposition 1. If necessary, the green indication can be inhibited duringsuch a sub-cycle.

The second position of the counter, during which an output is obtainedfrom gate 58, corresponds to the pedestrian interval of the controlperiod. During this interval a green indication is provided forvehicular traic and a walk indication is provided for pedestrian traic.During the third counter position an output is provided from gate 60 tocause a green indication for vehicular traliic and a clearance intervalfor pedestrians, during which the pedestrian indicators may provide aflashing dont walk or a flashing wait indication, for example.

In position 4 of the counter an output is generated by gate 62. Duringthis condition a green indication is provided for vehicular traiilc anda wait indication for pedestrians. This counter position corresponds tothe initial interval of the control period during which the intersectionmay be entered -by vehicles which had approached the intersection duringthe red indication and which were between the vehicle detector and theintersection waiting for right-of-way. Position 5 of the countercorresponds to the vehicle interval of the control period. In thisposition an output is obtained from gaate 64, and a green indication isprovided to vehicular traffic While a wait indication is provided topedestrians. The sixth position of the counter is a preparatory intervalduring which phase sequence unit 30 determines which phases of theintersection are to have right-ofway next, as will be more fullydescribed hereinafter. During this preparatory interval a signal isobtained from gate 66 to cause a green indication for vehicular traiiicand a wait indication for pedestrians.

In position 7 of the counter an indication is provided from gate 68 tocause a yellow or clearance indication for vehicular traffic and waitindication for pedestrians. This is the vehicle clearance interval. Theeighth counter position corresponds to the all red interval of thecontrol period during which a red indication is provided to allvehicular traffic and a wait indication to all pedestrians. In thisposition an output is provided from gate 70. The ninth counter positionis a transfer position during which a signal is provided from gate 72.In this position all the vehicular indicators provide a red indicationand the pedestrian signals provide wait indications. During thistransfer interval, transfer is made from the phase timing unit which hasjust completed its control period to the phase timing unit to which thenext control period is assigned.

The output of the last stage of counter unit 54 is connected to theinput of inverter 76 so that during counter positions 7, 8, and 9 asignal is applied to the input of inverter 76. Thus, when the counter isin any one of its positions 1-6, no input is applied to inverter 76, andso the inverter supplies an output signal. During these counterpositions 1-6 the vehicular traiiic is provided a green indication.Thus, any time this green indication is to be provided to the vehiculartraic, inverter 76 supplies a signal, referred to as the E Green signal.

When the traffic control system is iirst placed into operation, a startsignal is applied via line 77 to counter units 52 and 54 to set thecounter to its 7 position. This causes a signal from gate 68 to energizethe yellow indication for vehicular traiiic. Subsequent advance pulsesapplied on line 74 step the counter through its positions 8 and 9 inwhich the control period is transferred to another phase under thecontrol of phase sequence unit 30. The counter then returns to position1, the green skip posi tion. If there has been a pedestrian call on thephase to which r-ight-o-way has now been transferred, a signal passesthrough OR gate 78 to block INHIBITED-AND gate 79. The next advancepulse on line `89 passes through gate 80 to step the counter to itsposition 2 to provide a green indication for vehicles and a walkindication for pedestrians. At the conclusion of the pedestrianinterval, an advance pulse on lines 89 and 74 steps the counter toposition 3 to provide the pedestrian clearance interval. In thisposition a signal from gate 60 is applied to one input of AND gate 81and via OR gate 90 to the inhibit input of INHIBITED-AND gate 80. As aconsequence the next advance pulse on line 89 is blocked from line 74,and instead it passes through gate 81 and through OR gates 82 and 84 toset the counter to position 5. Thus, when a pedestrian call has resultedin the counter cycling through the pedestrian and pedestrian clearanceintervals of counter positions 2 and 3, the initial interval of position4 of the counter period is omitted, and the pedestrian and pedestrianclearance intervals replace it. The controller moves immediately to thevehicle interval of counter position 5 after the pedestrian clearanceinterval has terminated.

Position 5 is a rest position for the counter, and so it remains in thisposition until a command to step to another position is received. Duringcounter position 5, the signal from AND gate 64 passes to one signalinput of INHIBITED-AND gate 86. If there are no calls for rightof-wayfrom a conflicting traiiic phase assigned to the same interval sequenceunit, the E no call signal is also applied to a signal input of gate 86.If no call for right-ofway is present on a conflicting phase assigned tothe other phase sequence unit, the signal call away is not present atthe inhibit input of gate 86. Should a pedestrian call then be receivedon the phase which has right-of-way, a signal passes through OR gate 78to the third signal input of gate `86. Gate 86 then applies a signalthrough OR gate 90 to block gate 80. This same signal from gate 86 isapplied to the first input of AND gate 92. Via line 88 this conditionalso transmits the signal pedestrian return to the gating and timingcircuitry of FIG. 5 to cause an ad- Vance pulse on line 89, as describedmore fully hereinafter. This advance pulse is blocked at gate 80 andpasses through gate 92 to return the counter to its position 2, thusproviding a walk indication in response to that pedestrian call. Hence,the control system is capable of returning from its rest position in thevehicle interval to provide pedestrian right-of-way in the event of apedestrian call on the phase which has right-of-way when no conflictingcalls have been received.

If there has been no pedestrian call when the counter is in the greenskip interval at position 1, then during the time that the counter is inposition 1, the position 1 signal is applied from the output ofINHIBITED-AND gate 79 through OR gate 90 to block gate 80. This signalfrom gate 79 is also applied to the iirst input of AND gate 96. The nextadvance pulse therefore, passes through gate 96 and through OR gates 84and 98 to set the counter to position 4, providing a green vehicularindication and a wait pedestrian indication. This is the initialinterval of the rightof-way period, and so in the absence of apedestrian call, the pedestrian walk indication is omitted. Instead, thecontrol System steps from counter position 1 to the vehicle initialinterval in counter position 4, at the conclusion of which an advancepulse steps the counter position 5, the vehicle interval of theright-of-way period, where it rests. Hereinafter where it is stated thatthe counter steps to a position, it is meant that the counter moves tothat position in response to an advance pulse.

If the control system is next to provide right-of-way for a phaseconicting with that on which right-of-way is presently provided, thecounter next moves to position 6 either in response to an advance pulseor in response to the go to prep signal, as explained hereinafter.Position 6 is the green preparatory position during which position thephase sequence unit 30 determines the phase control unit or units towhich control is next to be assigned. At the termination of the greenpreparatory position, the counter steps to position 7 to provide thevehicle clearance interval on the phase from which right-of-way is being10 transferred. At the conclusion of the clearance interval, the counterprovides a brief all-red interval in its position 8. In position 9 theactual phase transfer takes place, following which the counter steps toposition 1 to provide control to the newly assigned phase.

In counter position 3, the pedestrian clearance interval, power isapplied to free-running multivibrator which then provides a flashingpower for causing the pedestrian clearance indicator to ilash in theevent no ilashing power is available within the indicator itself.

PHASE CONTROL UNITS-FIG 4; GATING AND TIMING CIRCUITS-FIG. 5

FIG. 4 depicts in detail block diagram form the circuitry of each phasecontrol unit 10i-24. Each phase control unit is associated with onetraic phase at the intersection and so receives input signals from avehicle detector, such as vehicle detector DA1, associated with traficphase A1. This vehicle detector, shown in FIG. 4 as vehicle detector102, applies -ground to the input of inverting amplifier 104 each time avehicle passes through its detection zone. The resulting positive pulsefrom ampliiier 104 passes through OR gate 106 to trigger locking delaymultivibrator 108. Locking delay multivibrator 108 is a monostablemultivibrator including a gate to provide memory when a locking input isapplied. Thus, with no locking input, a trigger input causes themultivibrator to assume its unstable state for a period of timedetermined by the time-constant of the multivibrator circuitry, just asin a one-shot multivibrator. With a locking input L, the multivibratorremains in its stable state until a trigger input is applied to it, atwhich time it assumes its` unstable state and remains there until thelocking input terminates. Following termination of the locking input,the multivibrator remains in its unstable state for a period of timedetermined by the time constant of its circuitry, after which it returnsto its stable state. This locking multivibrator is hereinafter calledDMV 108. A circuit suitable for this use is disclosed in FIG. 8 of U.S.patent application Ser. No. 586,881 tiled Oct. 14, 1966 by Charles L. DuVivier and Peter C. Brockett and assigned to the same assignee as thepresent application.

Each time a vehicle passes through the detection zone of vehicledetector 102, the one output of DMV 108 applies a pulse through OR gate110, INHIBITED-AND gate 112, and OR gate 114 to set phase memoryflip-flop (PMFF) 116 to its one condition. When the system is rst placedinto operation the start signal passes through OR gate 106 to have thesame effect as a vehicle detection pulse. The one output fromyKflip-liep PMFF 116l is applied through OR gate 117 to generate theoutput signal PMFFI, indicating that there has been a call forright-of-way on the traic phase associated with this phase control unit.This output is applied to phase sequence unit 30. When no call has beenreceived for this phase PMFF 116 is in its zero condition, and thesignal PMFFO is applied to AND gate 117 which provides the no callsignal to the interval sequence unit of FIG. 5 where it s summed withthe no call signals from other phases.

When the tratiic phase associated with this phase control unit is to bethe next traic phase to have right-ofway, as determined by phasesequence unit 30, the signal PNFFSI is applied to the set one input ofphase next ip-ilop (PNFF) 118. As a consequence PNFF 118 provides itsone output signal PNFFI as an input to AND gate 119. When the counterwithin the associated interval sequence unit reaches its position 1 atthe start of its next control cycle, a signal is applied to the otherinput of gate 119. Consequently, a signal passes from gate 119 to theset one input of phase flip-flop (PFP) 120. This switches PFP 120 fromits zero condition, in which it provides the output PFFI), to its onecondition in which it provides the output PFFI. During counter positions2 and 4 signals pass through OR gate 118 to reset PNFF 118 to its zerocondition. During counter position 9 the l l output of lgate 72 isapplied to the set zero input of PFF 120 to return the flip-flop to itszero condition. The PFP 1 output of PFF 120 is applied to one input ofAND gate 120.

Counter positions 2, 3, 4, 7 and 8 pertain to intervals of the controlsequence having fixed time durations for any one tratlic phase. Withineach phase control unit variable resistor 121 has one end connected toan input terminal to which a signal is applied from AND gate 58 when thecounter of FIG. 3 is in its position 2. Similarly within each phasecontrol unit a signal from gate 60 is applied to one end of variableresistor 122 during counter position 3; a signal from gate 62 is appliedto one end of variable resistor 123 during counter position 4; a signalfrom gate 68 is applied to one end of variable resistor 124 duringcounter position 7; and a signal from gate 7G is applied to one end ofvariable resistor 125 during counter position 8. The second end of eachof the variable resistors 121-125 comprise the inputs to OR gate 126which has its output connected to the first plate of capacitor 127. Thesecond plate of capacitor 127 is tied to ground.

When this phase control unit is not controlling rightof-way, the signalPFFtl from PFF 120 passes sequentially through -OR gates 128 and 130` tothe input of gating amplifier 132. When a signal is applied to the inputof gating amplifier 132, the amplifier Output is substantially -groundpotential, clamping capacitor 127 to that potential. With no input togating amplifier 132, its output line is open circuited, permittingvoltage to build up on capacitor 127 due to current through one of theresistors 121-125.

When this phase control unit is controlling the intersection, signalPFFG is not present, and so capacitor 127 is not clamped to ground.Then, during counter position 2, resistor 121 and capacitor 127 form acircuit which develops a voltage analog of the time duration of thepedestrian interval of the control sequence. Similarly, in counterpositions 3, 4, 7, and 8, the corresponding resistors 122-125 togetherwith capacitor 127 develop voltage analogs of the time durations of thecorresponding intervals of the control period.

The output of this interval timing circuit is obtained from the firstplate of capacitor 12-7 through diode 134 to output terminal 136 whichties it to terminal 138 Within the gating and timing circuitry of theassociated interval sequence unit, as shown in FIG. 5. From terminal 138the signal passes through OR gate 140 and I-NHIBITED- AND gate 141 toSchmitt trigger 142. Since the firing level of Schmitt trigger 142 isfixed, the time durations of the various intervals of the control periodare determined by the length of time required for the voltage analog oncapacitor 127 to reach this firing level. That length of time isdetermined by the adjustment of the corresponding variable resistor121-125. OR gate 140 also receives an input during counter position 1 tofire Schmitt trigger 142 during the green skip interval. The output ofSchmitt trigger 142 is tied to the input of direct coupled monostablemultivibrator 144 (hereinafter referred as direct coupled delaymultivibrator or DC DMV). Since the input to the DC DMV is directcoupled, its output signal is present so long as the input signal isapplied. Upon termination of the input signal, the DC DMV outputcontinues for a fixed length of time, similar to the operation of ACcoupled one-shot multivibrator upon application of a triggering pulse.The output from DC DMV 144 passes through OR gate 148, INHIBITED- ANDgate 150, and OR gate 152 to trigger monostable multivibrator orone-shot 154. The output of one-shot 154 is the advance pulse on line 89which causes counter units 52 and 54 to step through their countingcycle. Thus, it is seen that during those intervals of the controlsequence which have fixed time durations, the timing circuit comprisingone of the resistors 121-125, capacitor 127 and Schmitt trigger 142,operates with DC DMV 144 and one-shot 154, to provide the proper timeduration for that interval before generating the advance pulse.

OR gate 152 also receives an input on line 88 from gate 86 Within thecounter circuitry of FIG. 3 when a pedestrian call has been received onthe phase which is resting in its vehicle interval in the absence of acall from a conflicting phase. This input causes the advance pulse whichreturns the counter to its position 2 to provide a walk signal.

Within the timing circuitry of FIG. 5, the advance pulse obtained fromone-shot 154 is applied through OR gate 156, the output of which is theinterval timer reset signal that is transmitted to each phase controlunit. Within the phase control unit of FIG. 4 this interval timer resetsignal passes through OR gate to the input of gating amplifier 132,discharging capacitor 127 to ground.

So long as there is no call from a phase conflicting with that phasewhich has right-of-Way, then the signal 2 no call passes throughvINI-IIBITED-AND gate 162 in the interval sequence unit gating andtiming circuitry of FIG. 5. This signal then passes through OR gate 164,the output of which is the maximum timer reset signal which is appliedto each phase timing unit. The signals for counter positions 2, 3, and 4pass through O-R gate 166 in FlG. S to the inhibit input ofINHIBlTED-AND gate 168, which has the advance pulse applied to itssignal input. Thus, during the counter positions 2, 3, and 4 the advancepulse is blocked from passage through gate 168. The output of gate 168is tied to the input of OR gate 164 from which the maximum timer resetsignal is obtained.

As shown in FIG. 4, each phase control unit includes a maximum timer,comprising capacitor 170 and variable resistor 172 tied together betweena source of positive voltage and ground. When another phase control unitis controlling the intersection, the signal PFFG passes sequentiallyVthrough OR gates 128 and 174 to gating amplifier 176 which clampscapacitor 170 to ground, operating in the same manner as amplifier 132.Similarly, the maximum timer reset signal is applied through gate 174 togating amplifier 176 to discharge capacitor 170. When the intersectioncomes under control of this phase control unit, signal PFFU is no longerapplied to amplifier 176.

If no call for right-of-way has been received from a conflicting trafficphase, the signal E no call passes through gates 162 and 164 of FIG. 5,becoming the maximum timer reset signal. This signal passes through gate174 to gating amplifier 176, preventing voltage build-up on capacitor170. When a call is received from a conilicting traic phase assigned tothe same interval sequence unit, the signal E no call ends. When Va callis received from a conflicting traffic phase assigned to the otherinterval sequence unit, phase sequence unit 30 generates the signal callaway Which is applied through OR gate 177 to block gate 162. In eithercase the maximum timer reset signal ends, and voltage builds up oncapacitor 170 at a rate determined by the setting of adjustable resistor172.

This maximum time voltage on capacitor 170 of the phase control unit ofFIG. 4 is applied to the input of Schmitt trigger 178 Within the timingand gating circuitry of FIG. 5. When Schmitt trigger 17 8 fires, itsoutput activates DC DMV 180. The output of DC DMV 180 passes throughINHIBlTED-AND gate 181, becoming the signal go to preparatory. Thissignal is applied to line 181' of the interval sequence unit countercircuit (FIG. 3) to set the counter to its position 6, the preparatoryposition. The signal from gate 181 also passes through OR gate 156 and164, generating the interval timer reset signal and the maximum timerreset signal. Thus, this maximum timer determines the maximum length oftime for the part of the right-of-Way period overlapping positions 1-5of the counter for the phase holding the right-of-way 13 against a carwaiting on another phase, before the phase which has right-of-way isstepped to its green preparatory interval, position 6 of the counter.

In counter position 5, voltage is applied through variable resistor 182within the phase control unit of FIG. 4 to one side of capacitor 183,theother side of which is grounded. OR gate 184 receives as inputs thesignals from counter positions 2, 3, and 4. The output of OR gate 184 isapplied to the input of gating amplifier 18S so that during counterpositions 2, 3, and `4 gating amplifier 185 clamps capacitor 183 toground. Then, when the counter moves to position 5, gating amplifier 185unclamps the capacitor, and voltage passes through resistor 182 to buildup upon the capacitor 183. Each time a vehicle passes through thedetection zone of vehicle detector 102, DMV 108 sends a pulse through ORgate 110 and INHIBITED- AND gate 186 to the input of OR gate 184. As aconsequence amplifier 185 turns on to discharge capacitor 183. OR gate110 also receives an input directly from OR gate 106 so that if avehicle is moving very slowly through the detection zone of vehicledetector 102 capacitor 183 will be held discharged for as long as thevehicle is within the detection zone. The output of the E vehicle timercircuit is applied from capacitor 183 through diode 188 to Schmitttrigger 190 within the interval sequence unit gating and timingcircuitry of FIG. 5. The output of Schmitt trigger 190 is connected toone input of AND gate 192 which has the signal from gate 64 applied toits other input during counter position 5. Variable resistor 182 (FIG.4) is adjusted so that the length of time required for the voltage oncapacitor 183 to build up from ground potential to the firing level ofSchmitt trigger 190 is substantially the same as the average timerequired for a vehicle to travel from vehicle detector 102 through theintersection.

GAP MEASUREMENT TIMER-FIGURE 6 In counter position a voltage is appliedthrough resistor 194, shown in FIG. 6, to the first plate of capacitor196 which has its second plate tied to ground. Thus, voltage builds upon capacitor 196. This voltage is applied through impedance converter198 and resistor 200 to junction 202 which is tied to the input ofSchmitt trigger 204. Impedance converter 198 acts as a buffer with highinput impedance. When there is no call for right-of-way from aconfiicting tratiic phase assigned to the same interval sequence unit,the signal 2 no call is applied to the signal input of INHIBITED-ANDgate 205. If a call for right-of-way is present from a conflictingtraffic phase assigned to the other interval sequence unit, the signalcall away blocks gate 205. Thus, in the absence of calls for contiictingright-of-way, a signal from gate 205 passes through OR gate 206 to theinput of gating amplifier 208. As a consequence, amplifier 208 clampscapacitor 196 to ground. When such a conicting call is received, thisinput to gate 206 terminates, and voltage commences to build up oncapacitor 196. When a phase control unit is controlling theintersection, the signal PFFl is applied to the first input of its ANDgate 209, shown in FIGURE 4. Each time a vehicle passes through thedetection zone of vehicle detector 102, DMV 108 sends a pulse through ORgate 110 to the other input of gate 209. Coincidence of these two inputscauses gate 209 to generate a gap reset signal which is applied to the 2gap reset input of OR gate 206 in FIG. 6. Thus, capacitor 196 isdischarged each time a vehicle passes through the detection zone of thevehicle detector on a phase which is in control of the intersection. Asa consequence, the voltage on capacitor 196 is a measure of the timespacing or gap between consecutive vehicles on that traffic phase.

During counter position 5, voltage also passes through variable resistor210, within the phase control unit of FIG. 4, to the first plate ofcapacitor 212 which has its second plate tied to ground. So long asthere is no call for right-of-way from a confiicting trafiic phase, thecall away signal does not block INHIBITED-AND gate 213, and

so the 2 no call signal passes through gate 213 and through OR gate 214to turn on gating amplifier 215 which clamps capacitor 212 to ground.Amplifier 215 is also held on by the signal PFFO via gates 128 and 214when the intersection is under control of another traffic phase. Once aconliicting call is received, the output of gate 213 terminates, and sovoltage commences to build up on capacitor 212. This voltage passesthrough diode 216 within the phase control unit to the E gap reductiontimer input of impedance converter 217 within the interval sequenceunit, as shown in FIG. 6, The output of impedance converter 217 iscoupled through resistor 218 to junction 202 and thus to the input ofSchmitt trigger 204. The voltage at junction 202 is a function of thesum of the voltage applied to the input of impedance converter 198 andthe voltage applied to the input of impedance converter 217. Thisvoltage at junction 202 is applied to the input of Schmitt trigger 204.The voltage at the input of impedance converter 217 continuallyincreases after a confiicting right-of-way call is present during thevehicle interval (counter position 5). As the voltage at the input ofimpedance converter 217 increases, the difference between this voltageand the firing level of Schmitt trigger 204 decreases. This voltagedifference represents the minimumV permissible gap between vehicleswhich will be permitted to retain right-of-way on this traffic phase.Hence the minimum permissible gap length continuously decreases once aconflicting call is received during the vehicle interval. When thevoltage at the input of impedance converter 198 represents a gapexceeding the permissible minimum (i.e. the voltage at junction 202exceeds the firing level of Schmitt trigger 204), Schmitt trigger 204fires, and its output passes through INHIBIT- ED-AND gate 219 to setflip-iiop 220 to its one condition, thereby generating the signal lastvehicle passage (LVP). This signal indicates that traffic on the phasehaving the right-ofway has reached such a light level that the gapsbetween consecutive vehicles exceed the minimum permissible gap, and soit is time to transfer right-of-way to the next phase which is awaitingit. OR gate 221 receives the hold signal and the counter position 1signal at its input. The output of gate 221 is connected to the set zeroinput of flip-fiop 220, so that when the LVP signal causes transfer ofright-of-way, flip-Hop 220 is reset to its Zero condition during counterposition 1 of the next traffic phase.

The LVP signal is applied to the inhibit input of gate 186 within thephase control unit of FIG. 4. As a consequence, subsequent vehiclespassing detector 102 do not cause capacitor 183 to be discharged.Therefore, the voltage at capacitor 183 increases until it reaches thefiring level of Schmitt trigger 190, shown in FIG. 5 within the intervalsequence unit. The output of Schmitt trigger passes sequentially throughgates 192, 140, and 141 to activate Schmitt trigger 142 which turns onDC DMV 144. The DMV 144 output passes sequentially through gates 148,150, and 152 to activate one-shot 154 which generates the advance pulse.This steps the counter of FIG. 3 to its position 6, the preparatoryposition.

Within the phase control unit of FIG. 4 voltage is applied throughvariable resistor 222 to one plate of capacitor 224 which has its otherplate grounded. When this phase control unit is not controlling theintersection, the signal PFFO passes through OR gate 226 to turn ongating amplifier 228, clamping capacitor 224 to ground. When this phasecontrol unit is controlling the intersection signal PFFO ends. Each timea vehicle passes detector 102, DMV 108 sends a pulse through gates 110and 226 to turn on amplifier 228, thereby discharging capacitor 224.This discharging of cap-acitor 224 is not inhibited by the LVP signal.Thus, the voltage on capacitor 224 is a measure of the length of timewhich has elapsed since a vehicle has passed detector 102. The voltageon capacitor 224 passes through isolating diode 230 to the E passagetimer input of Schmitt trigger 232 within the passage timing circuitryof FIG. 7. Schmitt trigger 232 has its output connected to the input ofinverting amplifier 234, the output of which is tied to one input of ANDgate 236. At its other input, gate 236 receives a signal from gate 68during counter position 7, the vehicle clearance interval. Schmitttrigger 232 turns on when the voltage on capacitor 224 indicates thatsuicient time has elapsed since passage of a vehicle past detector 102for that vehicle to have entered the intersection. Thus, whenever avehicle is between detector 102 and the intersection, amplitier 234applies an enabling input to gate 236. If that enabling input is presentwhen counter position 7 is reached, a signal is generated by gate 236 toindicate that a vehicle will be waiting for right-of-way on this traicphase after right-of-way has been removed from the phase. Within thephase control unit of FIG. 4, this vehicle waiting signal is applied toone input of AND gate 238 which receives the signal PFFI at its otherinput. Gate 238 then sends a signal through OR gate 114 to set the phasememory tlip-op PMFF 116 to its one condition which indicates thatright-of-way is to be returned to this traffic phase in its turn.

In the event that both phases on which right-of-way is present havereached their counter position number 5 and are to lose right-of-way,then a gap in the traffic ow on one phase in excess of the acceptablegap duration determined by the tiring level of Schmitt trigger 204 (FIG.6) initiates that tralc phase stepping from counter position 5 tocounter position 6. Gating circuitry within the phase sequence unit 30,to be discussed later, causes that tratlic phase to rest in this greenpreparatory counter position 6 until the other traffic phase has alsoreached its preparatory condition. The vehicle timing circuitrycomprising resistor 182 and capacitor 183 insures that the last vehicleto pass the vehicle detector of the last traffic phase to come to thepreparatory condition, has suflicient time to clear the intersection.However, since the other traic phase is resting in counter position 6,its vehicle timing circuit is not operating. Consequently, if a vehiclecrosses its vehicle detector just before the second traiiic phasereaches its preparatory position, there might be insucient time for thatvehicle to clear the intersection. In such an event, the passage timercomprising resistor 222 and capacitor 224 results in a signal beingapplied from gate 236 through gate 238 and gate 114 to set the phasememory tlip-tlop PMFF 116 so that right-of-way will be recalled to thattraic phase. This insures that that Vehicle will not be trapped on atraffic phase to which right-of-way will not be returned.

The counter position 5 signal and the counter position 6 signal passthrough OR gate 240 (FIG. 4) to the first input of AND gate 242 whichreceives the PFF1 signal at its second input. The output of gate 242passes through OR gate 244 to reset phase memory flip-flop PMFF 116 toits zero condition. Thus, PMFF 116 is reset during interval 5 of thecontrol sequence and is held reset during position 6. In addi-tion, the2 green signal and the PF1-il signal pass through INHIBITED-AND gate246, except with the LVP signal is applied to the inhibit input of gate246. The output of gate 246 passes through OR gate 248 to block gate 112so that. detector pulses cannot pass to the set one input of PMFF 116.If it is desired to provide the option of automatic recall ofright-of-way to this traic phase, the PFFO signal is applied to oneContact of a vehicle recall switch 247, the other contact of which isapplied through OR gate 114 to the set one input of PFF 116, as shown inFIG. 4.

Determination of which traffic phases are next to be allocatedright-of-way takes place during the counter position 6 for those phaseswhich are losing right-Of-way.. Thus, if a street change is to be made,requiring that bolh phases lose r-ight-of-way, the determination is madeduring the time that both counters are in their position 6. If onetransfer is to be made on the salme street, then the determination ismade when that one counter is in its position 6. To insure againsterroneous indications during the brief time that the determination ismade, the DMV 1.08 within each phase control unit is locked so thatact-uations from vehicle detectors cannot be passed. Circui.ry withinthe phase sequence unit 30 generates the lock detector signal which isapplied to each DMV 108 and through each OR gate 248 to the inhibitinput of each IN- HlBITED-AND gate 112. When this signal is present, DMV108 becomes a memory device. Thus, if at the time the lock detectorsignal is applied, DMV 108 is in its zero condition, it remains so untila vehicle detection pulse is applied to its set input from OR gate 106.Application of that pulse causes DMV 108 to assume its one condition,and it is locked in that one condition so long as the lock detectorsignal is present. Thus, DMV 108 remembers that a vehicle has passed itsvehicle detector while the lock detector signal is present. When thecouner steps out of its position 6 the lock detector signal ends, undthe output from DMV 108 passes sequentially through gates 110, 112, and114 to set PMFF 116 to its one condition, thereby indicating that avehicle is waiting for rightof-way on that traic phase.

During the time that the counters in` both interval sequence units arein their positions 6, signals are applied through gating circuitrywithin the phase sequence unit to be described later to set the phasenext flip-flop PNFF 118 with-in the phase control units of the nexttrafc phases which are to have right-of-Way. Phase control unit 30 thentransmits the signal preparatory leave (PL) which is applied to OR gateWithin the gating and timing circuitry (FIG. 5) of each intervalsequence unit. This signal passes through OR gate 140, to cause theadvance pulse from one-shot 154. As a consequence, the counter of FIG. 3steps to its counter position 7, the vehicle clearance interval.

The vehicle clearance interval and the all-red interval of counterpositions 7 and 8 are timed for durations determined by resistors 124and 125, respectively, together with capacitor 127, and then the counterreaches its position 9, the transfer position. During counter position 9phase sequence unit 30 generates a transfer signal which is applied toeach interval sequence .unit which is to start a new cycle. Thus, ifright-of-way is on tirst and second non-conicting tratiic phase and isto be transferred from the second phase to a third phase which is alsonon-conflicting with the first, the transfer signal is applied only tothe interval sequence unit associated with the second and third phases.If instead right-of-way is to-be transferred to traic phases conictingwith both `the tirst and second phases, the transfer signal is appliedto both interval sequence units.

The transfer signal, shown in FIG. 5 as signal TR, is applied to OR gate140 to turn on Schmitt trigger 142,

thereby causing one-shot 154 to generate an advance.

pulse. The TR signal is also applied through OR gate 166 to block gate168 from passing the advance pulse to OR gate 164.

During the vehicle interval the counter position 5 signal from gate 64(FIG. 3) passes through INHIBITED-AND gate 250 (FIG. 5) and OR gate 252to the first input of AND gate 254. It there are no calls forright-of-way from traffic phases conicting with this tratlic phase, thenINHIBITED-AND gate 256 passes a signal through OR gate 258 to the secondinput of gate 254. On coincidence of lthese two signals at gate 254,a'signal is applied to block gate from activataing one-shot 154 whichgencrates the advance pulse. Thus, when trafc on all phases is extremelylight, and the vehicle timer (comprising resistor 182, capacitor 183,and Schmitt trigger turns on Schmitt trigger 142, no advance pulse canbe gener'- ated, unless there is actually a call for right-of-way from aconilcting tra'ic phase. As a consequence, the system will not slowlychange back and forth, providing right-of- Way on one traflic phase andthen on another tratlic phase during these extremely light traicconditions.

Within the phase control unit of FIG. 4, the signal PFFO passes throughOR gate 260 to output line 262 which energizes the red indicator withintrafiic signal 263 for this trafiic phase. The E green signal frominverter 76 associated with the counter circuitry is applied to oneinput of AND gate 264 within each phase control unit. When this phasecontrol unit is controlling the intersection, the signal PFFI is appliedto the second input of gate 264. As a consequence, gate 264 provides asignal on its output line 266 which is applied to the trafiic signal 263at the intersection for this traiic phase to cause the green indication.AND gate 268 receives as inputs the signal PFFl and the signal from gate68 during the counter position 7, the vehicle clearance interval. Oncoincidence of these two inputs, gate 268 provides a signal on outputline 270 which ties to the traic signal 263 for this phase to cause theyellow indication. Lines 266 and 270 connect respectively to inverters272 and 274 which have their outputs applied to the two inputs of ANDgate 276. The output of AND gate 276 connects through OR gate 260 tooutput line 262 to cause the red indication during counter positions 8and 9 when this phase control unit is controlling the intersection.

If this phase control unit is associated with one of the A trafficphases, which require pedestrian indications, then the pedestrianpush-button shown in FIG. 4 as pedestrian push-button 278, is connectedas an input to inverting amplifier 280. inverting amplifier 2-82receives the lock detector input when the control system is determiningwhich trafiic phase is next to be assigned rightof-way. Inverters 280and 282 have their outputs applied to the two inputs of AND gate 284,thus inverter 282 applies a signal to gate 284 at all times exceptduring the lock detector condition. Consequently, any time a pedestrianpush-button is activated, except during this brief interval, inverter280 passes a signal through gate 284 to OR gate 286 which applies thesignal to the set one input of pedestrian phase memory flip-flop (PPMFF)288. The start signal received when the control system -rst commencesoperation is also applied as an input to OR gate 286. Similarly, if itis desired to provide automatic recall to the pedestrian indications onthis trafiic phase, then the signal PFFO is connected to one terminal ofa pedestrian recall switch 289 which has its second terminal connectedto the input of OR gate 286, as depicted in FIG. 4.

The one output of PPMFF 288 is connected as an input of OR gate 117,which also receives an input from the one output of PMFF 116. The outputof OR gate 117 is the PMFFl signal, indicating that a call has beenreceived for right-of-way on this trafiic phase. The one output of PPMFF2-88 is also connected as an input to AND gate 290 which receives thesignal PFFl as its other input. When these two inputs are applied togate 290, the gate generates the pedestrian call signal for this phasewhich passes through isolating diode 292 to 2 pedestrian call circuitry.INHIBITED-AND gate 294 has its signal input tied to the one output ofPPMFF 288 and its inhibit input connected to the one output of PFF 120.The output of gate 294 passes through inverting amplifier 296 to oneinput of AND gate 117'. Thus, in the absence of a call for pedestrianindications on this phase, no signal is applied from gate 294 toinverter 296. As a consequence the inverter 296 applies an input to gate117'. If there has been no vehicle call for this phase, then PMFF 116applies its zero output to the other input of gate 117', and gate 117generates the no call signal for this phase which is applied throughsumming diode 297 to the E no call circuitry. When a pedestrianactuation has been received to set PPMFF 288 to its one condition, asignal is applied by gate 294 to inverter 296. As a consequence, theoutput from inverter 296 to gate 117 ends, and so the 2 no call signalis terminated. When this phase control unit is controlling theintersection,

18 then signal PFFI inhibits gate 294, and so inverter 296 again appliesa signal to gate 117.

AND gate 298 receives a signal from gate 58 during counter position 2 atits first input and receives the PFFI signal from PFF 120 at its secondinput. Coincidence of these two inputs causes gate 298 to generate asignal on output line 300 to cause the pedestrian indicator 301 toprovide the walk indication for the pedestrians on this tratiic phase.The output of gate 298 also resets PPMFF 288 to its zero condition. ANDgate 302 receives a signal from gate 60 during counter position 3 at itsfirst input and receives the signal PFF1 from PFF 120 at its secondinput. Coincidence of these two signals causes gate 302 to generate asignal on its output line 304 to cause the pedestrian indicator 301 toprovide the pedestrian clearance indication for this trafiic phase.Output lines 300 and 304 are connected respectively through inverters306 and 308, each of which has its output tied to an input of AND gate310. The output of gate 310 is connected as one input to OR gate 312.INHIBITED- AND gate 314 receives the PFFI o-utput from PFF 120 at itssignal input. The inhibit input of gate 314 is connected to the outputof yfree-running multivibrator within the counting circuitry of FIG. 3to receive flashing power during counter position 3. The output of gate314 is connected to the input of inverter 316 which has its output tiedto the second input of OR gate 312. The output of OR gate 312 isconnected to output line 318 which causes the wait indication on thepedestrian indicator 301 for this trai-lic phase. If the pedestrianindicator utilized with this traffic phase has its own flashing power,then gate 314, inverter 316 and OR gate 312 can -be omitted, with theoutput line 318 taken directly from AND gate 310. Then during thepedestrian clearance interval of counter position 3, the pedestrianclearance indication on output line 304 activates this source offiashing power within the pedestrian indicator to cause a iiashing dontwalk or flashing wait indication for pedestrians. If the pedestrianindicator does not have its own source of ashing power, then output line304 is not connected to the pedestrian indicator, but instead gates 312and 314 and inverter 316 are provided as depicted in FIG. 4. Duringcounter position 3 the lflashing power interrupts the application of thesignal applied to gate 314. An intermittent signal on line 318 thencauses the dont walk or wait indicator to flash on the pedestrianindicator 301. During all counter positions except counter positions 2and 3 for this traiiic phase, inverters 306 and 308 both apply signalsto AND gate 310 which then passes an indication through gate 312 tocause the wait indication to appear on the pedestrian indicator 301. Forthe phase control units associated with the B trafiic phases which donot require pedestrian indications, the components 117, 117', and278-318 of FIG. 4 are omitted.

PHASE SEQUENCE UNIT COMMON CIRCUITRY FIGURE 8 FIG. 8 depicts circuitrywithin phase sequence unit 30 which determines when the counters withineach interval sequence unit are to be stepped out of the preparatoryinterval of counter position 6 to the clearance interval of counterposition 7. If a street change is to be made, this phase sequence unitcommon circuitry synchronizes operation of the two counters, therebyinsuring that the right-of-way periods end at the same time on bothtraffic phases of the street losing right-of-way.

When the green right-of-way for a trafiic phase is to end, a preparatoryleave signal is generated within this common circuitry. A preparatoryleave signal is generated for each interval sequence unit. These signalsare shown as signal ISO-PL, obtained from AND gate 402 to signify thatthe odd interval sequence unit should leave its preparatory position,and as signal ISE-PL obtained from AND gate 404 to signify that the eveninterval sequence unit should leave its preparatory position.

Under extremely light traic conditions, right-of-way might be assignedfor a long period of time to the two straight-through tratiic phases ofone street, for example, phases A1 and A2 of street I, with eachinterval sequence unit resting in its counter position 5. If there isthen received a call for right-of-way from only one coniiicting traicphase such as phase A3, both interval sequence units step sequentiallythrough their positions 6, 7, and 8 to position 9, the transferposition. The odd interval sequence unit associated with phase controlunit A3 then steps to its position 1 to assign right-of-way to traicphase A3. However, there has not been a call for right-of-way on anyeven traiiic phase and so the even interval sequence unit does not havea phase control unit requiring right-ofway. Accordingly, the eveninterval sequence unit rests in counter position 9, the transferposition. This condition of having right-of-way assigned to only onetraic phase is referred to as single-ended operation as distinguishedfrom double-ended operation in which right-of- Way is simultaneouslyprovided to two non-coniiicting traffic phases. The phase sequence unitcommon circuitry of FIG. 8 includes flip-flop 400 which is set to itsone condition when single-ended operation results in right-ofway beingprovided for an even trai-lic phase but not for an odd traic phase,Thus, ip-iiop 400 is referred to as the odd interval sequence no callhip-flop (ISONCFF), and it provides the signal ISONCFFI during evenphase single-ended operation. Similarly, iiip-ilop 401 is the eveninterval sequence no call flip-flop (ISENCFF) and it provides the signalISENCFF 1 during odd phase single-ended operation.

R gate 405 receives as inputs the one output of the phase next hip-flop118 in each odd phase control unit. Thus, gate 405 receives as inputsthe signals AIPNFFI, BlPNFFl, A3PNFF1, and BSPNFFI. In addition, whenthe traic control system is in even phase single-ended operation, ORgate 405 receives as an input the signal ISONCFFI from the no callflip-Hop 400 for the odd interval sequence unit. The output of gate 405is applied as an input to AND gate 402. The second input to gate 402 isthe counter position 6 signal ISO(6) from gate 66 within the oddinterval sequence unit. On coincidence of these two inputs to gate 402,the gate generates the signal ISO-PL, causing the odd interval sequenceunit to leave its preparatory position. In like manner, OR gate 406receives as inputs the signals A2PNFF1, BZPNFFI, A4PNFF1, and B4PNFF1from the phase next flip-Hop 118 Within each even phase control unit. Inaddition, OR gate 406 receives the input signal ISENCFFI during oddphase single-ended operation, when there is no even phase control unitcontrolling the intersection. The output of gate 406 is connected as aninput to AND gate 404. When the counter within the even intervalsequence unit is in its position 6, gate 404 receives the ISE(6) signalfrom AND gate 66 within that even interval sequence unit. Ou coincidenceof these two inputs, gate 406 generates the ISE-PL signal, indicatingthat the even interval sequence unit is to leave its preparatoryposition.

The preparatory leave signal PL is applied to OR gate 140 within thegating and timing circuitry of FIG. 5, causing one-shot 154 to generatethe advance pulse.

STREET CHANGES The one output of the phase memory flip-op 116 associatedwith each street II traffic phase is applied as an input to OR gate 408,shown in the upper left of FIG. 8. Thus, gate 408 receives the signalA3PMFF1, A4PMFF1, BSPMFFI, and B4PWFF1. The output of gate 408 is thesignal 34-4 call. This signal is applied to each set of phase selectioncircuitry for use as depicted in FIG. 9. In addition, the output of gate408 is connected to the input of inverter 409 which has its gutputapplied to each set of phase selection circuitry to provide the signalTS-(, ca ll when there is ne input t0 gate 408.

The output of gate 408 is connected as an input to AND gate 410. Gate410 also receives as inputs the signals A1PFF1 and ISO(16). Thus, whenright-of-way is on phase A1 and the odd interval sequence unit hasstepped to its preparatory position, a call for right-of-way from anystreet II traiiic phase results in a signal passing from gate 410through OR gate 412 to the rst input of AND gate 414. AND gate 416receives as inputs the signals BIPFF 1 AIPMFFO, and ISO(6). Thus, ifright-of-way is on phase B1 and there has been no call for right-of-wayfrom phase A1, but the odd interval sequence is in its preparatoriposition, then gate 416 generates a signal which also passes through ORgate 412. to the first input of AND gate 414.

AND gate 418 receives as inputs the signals A2PFF1, lSE(6), and 3+4call. Therefore, if right-of-way is on traflic phase A2, and there hasbeen a call for right-ofway from a street II traffic phase, and the eveninterval sequence unit is in its preparatory position, gate 418 passes asignal through OR gate 420 to the second input of AND gate 414.Likewise, AND gate 422 receives as inputs the signals BZPFFI, A2PMFFO,and ISE(6). Therefore, if right-of-way is on traffic phase B2 and therehas not been a call for right-of-way from phase A2 Ibut the eveninterval sequence unit is in its preparatory position, then gate 422generates a signal which also passes through OR gate 420 to the secondinput of AND gate 414.

Coincidence of the two inputs to AND gate 414 indi- Cates thatright-of-Way is on traffic phases found on street I and is about to betransferred to traic phases of street II` In this condition, gate 414passes a signal through OR gate 424 which is then applied to OR gate426. The output of gate 426 is the lock detector signal applied to thevehicle detector DMV 108 via OR gate 248 to the inhibit input of gate112 within each phase control unit to prevent the output of DMV 108 frompassing during the preparatory interval.

The output of OR gate 424 is also applied to the input of time delay 428which provides a delay in the order of 40 milliseconds. The output ofdelay 428 is applied to the input of Schmitt trigger 430. The Schmitttrigger 430 output is the signal street I to street II change. Thissignal indicates that right-of-way is to be transferred from street I tostreet II and is applied to each set of phase selection circuitry foruse as shown in FIG. 9. Within the phase selection circuitry the streetI to street II change signal is utilized to cause the commands which setto the one condition the phase next ilip-op 118 within the appropriatephase control unit, as explained more fully hereinafter with referenceto FIG. 9. Time delay 428 is provided to insure that each DMV 108 haslocked before the phase selection circuitry decides which phase nextip-ilops are to be set.

A corresponding set of circuitry is provided to gencrate the street IIto street I change signal. Thus, OR gate 432 receives as inputs thesignals AIPMFFI, AZPMFFI, BIPMFFI, and BZPMFFI from the phase memoryflip-flops within each street I phase control unit. These signals arepresent Whenever a call for right-ofway is received on the associatedstreet I trafiic phase. The output of gate 432 is the signal 1+2 callindicating that a call for right-of-way has been received from one ofthe street I traic phases.

.This signal is applied to each set of phase selection circuitry for-use as depicted in FIG. 9. In addition, the output of gate 432 isconnected to the input of inverter 434 which has its output applied toeach set of phase selection circuitry. This output is the signal -lomwhich is present when there is no input to gate 432.

The .output of OR gate 432 is also connected as an input to AND gate436. Gate 436 also receives as inputs the signals A3PFF1 and ISO(6).Thus, when right-of-way is on trafc phase A3 and a call for right-o-Wayhas been received from one of the street I traiiic phases and the oddinterval sequence unit is in its preparatory position, gate 436 passes asignal through O R gate 438 t0 the 21 first input of AND gate 440. ANDgate 442 receives as inputs the signals B3PFF1, ASPMFF() and ISO(6).Therefore, when right-of-way is on traffic phase B3 and there has not`been a call for right-of-way on traic phase A3, but the odd intervalsequence unit is in its preparatory position, gate 442 provides a signalwhich also passes through OR gate 438 to the first input of AND gate440.

AND gate 444 receives as input the signals A4PFF1, ISE(6), and l-t-Zcall. Thus, if trafc phase A4 is providing right-of-way and a call isreceived for right-ofway from a traic phase on street I and the eveninterval sequence unit is in its preparatory position, a signal fromgate 444 passes through OR gate 446 to the second input of AND gate 440.AND gate 448 receives as inputs the signals B4PFF1, A4PMFFO and ISE(6).Therefore, if right-of-way is on traic phase B4 and there is no call forright-o-way from trafic phase A4, but the even interval sequence unit isin its preparatory position then gate 448 provides a signal which alsopasses through OR gate 446 to the second input of AND gate 440.Coincidence of these two inputs to -gate 440 indicates that right-of-wayis on street II and is to be transferred to street I. In this condition,gate 440 provides a signal which passes through OR gate 450 to OR gate426. The output of OR gate 426 is the lock detector signal which causesthe DMV 108 within each phase control unit to lock, as described above.

The output of gate 450 also is connected to the input of time delay 452,which may be in the order of 40 milliseconds. The output of time delay452 is connected to Schmitt trigger 454 which provides as its output thesignal street II to street I change. This signal is applied to each setof phase selection circuitry for use as depicted in FIG. 9. This signalpasses through gating within the phase selection circuitry to cause theappropriate phase next ip-op to be set to its one condition;

If a single-ended call for right-of-way has been received, then only onephase next Hip-flop will be set to its one condition. For example, ifright-of-way is on traic phases A1 and A2 when a call for right-of-wayis received from traffic phase A3, then the street I to street II changesignal is generated and passes through logic within the odd phaseselection circuitry of FIG. 9 to cause the phase next ilip-op withinphase control unit A3 to be set to its one condition. As a consequencethe signal A3PNFF1 is applied through OR gate 405 to AND gate 402. TheISO(6) signal is also applied to AND gate 402, and so gate 402 generatesthe signal ISO-PI., causing the counter within the odd interval sequenceunit to leave its preparatory position and to commence the vehicleclearance interval of counter position 7. However, since there has notbeen a call for right-of-way from au even traffic phase, the even phaseselection circuitry does not cause any of the phase next ip-ops withinthe even phase control units to be set to their one condition.Accordingly, there is no signal from any of the phase next ip-opsapplied to OR gate 406. In the condition described in the illustrativeexample above, gate 418 provides a signal through OR gate 420 to oneinput of AND gate 456. The street I to street II change signal is alsoapplied to gate 456. Since there has not been a call for right-of-way oneither phase A4 or phase B4, both the A4PMFFO signal and the B4PMFFOsignal are applied to gate 456. As a consequence, gate 456 generates asignal which passes through OR gate 458 to set to its one conditionISENCFF 401, the no-call ilip-op associated with the even intervalsequence unit. This provides the signal ISENCFFI which passes through ORgate 406 to AND gate 404. Since the even interval sequence unit is inits preparatory position, the signal ISE(6) is also applied to gate 404,and so gate 404 provides the ISE-PL signal, causing the even intervalsequence unit to leave its preparatory position, and to enter thevehicle clearance interval of counter position 7.

In like manner, if right-of-way is on street II when a call forright-of-way is received from a single street I tralic phase, such astrafc phase A1, then the output of gate 446 is applied to the input ofAND gate 460. The street II to street I change signal is also applied togate 460. Since there has not been a call for right-ofway from eitherphase A2 or phase B2, both the signal A2PMFFO and the signal B2PMFFO areapplied to gate 460. As a consequence, gate 460 generates a signal whichpasses through OR gate 458 to the set one input of ISENCFF 401. Thus,the system is again placed in singleended operation.

When the system returns to double-ended operation, the even intervalsequence unit steps to its counter position 1, and inverter 76 withinthe even interval sequence unit applies the ISE E green signal to thesignal input of INHIBITED-AND gate 462. During the preparatory positionof the even counter, the ISE(6) signal is applied to the inhibit inputof gate 462. Thus, when the green indication is returned to an eventraflc phase, gate 462 generates a signal which returns ISENCFF 401 toits zero condition.

In like manner, when the system is in single-ended operation on an eventraic phase, ISONCFF 400, the no call flip-lop for the odd intervalsequence, is set to its one condition. Thus, the output of OR gate 412is applied as an input to AND gate 464 which also receives as inputs thesignals A3PMFFO, B3PMFFO, and street I to street II change. The outputof gate 464 passes through OR gate 466 to the set one input of ISIONCFF400. Consequently, the signal ISONCFFI passes through OR gate 405 to thevfirst input of AND gate 402, and so when even phase single-endedoperation is to take place, this input enables gate 402 to transmit thesignal ISO-PL to cause the odd interval sequence unit to leave itspreparatory position. The output of OR gate 438 is connected as an inputto AND gate 470 which also receives as inputs the signals A1PMFFO,B1PMFFO, and street II to street I change. The output of gate 470 passesthrough OR gate 466 to cause ISONCFF 400 to assume its one condition.When double-ended operation is resumed and the green indication isprovided for an odd traic phase, the output of inverter 76 within theodd interval sequence unit is applied as the ISO E green signal input toINHIBITED-AND gate 472. During the odd counter position 6 the signalISO(6) is applied to the inhibit input of gate 472. Thus, when the greenindication is returned to an odd traffic phase, the output of gate 472is applied to the set zero input of ISONCFF 400 to return the iiipop toits zero condition.

The transfer from single-ended operation on one street to double-endedoperation on the other street requires that the appropriate streetchange signal be generated. Accordingly, OR gate 474 in FIG. 8 receivesas inputs the counter position 9 signals from both the odd intervalsequence unit and the even interval sequence unit and applies its outputto AND gate 476. OR gate 478 receives the counter position 6 signal fromboth interval sequence units and `applies its output to AND gate 476. ORgate 480 receives the one output from both no call ip-op; thus itreceives as inputs the signals ISONCFFl and ISENCFFI. The output of gate480 is connected to an input of AND gate 476. OR gate 482 receives asinputs the B/A call signals from each set of phase selection circuitry.This signal is generated in each set of phase selection circuitry whenright-of-way on a left-turn traic phase is to be terminated andtransferred to straightthrough trafc from the opposite direction on thesame street, as more fully explained hereinafter with reference to FIG.9.

The output of gate 482 is connected to the input of inverter 484 whichhas its output tied to an input of AND gate 476. The output of gate 476is applied as an input of AND gate 486 which also receives as inputs thesignals A3PFFO, B3PFFO, A4PFFO, and B4PFFO. Thus, if right-of-way is ona street I traffic phase, these latter four signals are applied to gate486. During single-ended operation the interval sequence unit associatedwith the traflic phases which are not providing any right-of-Way is inits counter position 9, and so a signal passes from gate 474 to gate476. One of the no call flip-flops 400 or 401 is in its one condition,and so a signal passes from gate 480 to gate 476. When the trafhc phasewhich is providing right-of-Way reaches its counter position 6, a signalpasses from gate 478 to gate 476. If right-of-Way is to be transferredto another street, then there is no B/A call signal, and so inverter 484applies a signal to gate 476. Consequently, gate 476 applies a signal togate 486, and so gate 486 passes a signal through OR gate 424 to gate426 to cause the lock detector signal. In addition, this v signal passesfrom gate 424 to time delay 428 which introduces a short delay beforeturning on Schmitt trigger 430 to generate the street I to street IIchange signal.

In like manner, the output of gate 476 is applied to gate 488 whichreceives the signals A1PFFO, B1PFFO, AZPFFO, and BZPFF() as inputs.Thus, if the system is in single-ended operation on a traffic phase ofstreet II, and it is to change to a street I trahie phase, gate 488provides a signal which passes through OR gate 450 to gate 426 where itbecomes the lock detector signal. In addition, the signal from gate 450is applied. to time delay 452 which introduces a short delay beforeturning on Schmitt trigger 454 to generate the street II to street Itransfer signal.

These street change signals are applied through gates Within each set ofphase selection circuitry to set to the one condition phase nextflip-flop 118 Within the appropriate phase control units.

PHASE SELECTION CIRCUITRY--FIGURE 9 FIG. 9 depicts the odd phaseselection circuitry within phase sequence unit 30. This odd phaseselection circuitry determines which odd trailic phase is next to beassigned right-of-way. A corresponding set of circuits is providedwithin the even phase selection circuitry to receive the correspondinginput signals and to provide the corresponding output signals.

AND gate 502 Within the odd phase selection circuitry of FIG. 9,receives as an input the signal BIPFFI when the phase control unitassociated with tralc phase B1 is controlling the intersection. Thesecond input of gate 502 receives the signal AlPMFFl when a call forright-of- Way has been received from trahie phase A1. The last input ofgate 502 receives a signal from AND gate 66 within the odd intervalsequence unit during odd counter position 6. This signal is designatedISO(6) and exists during the green preparatory period. Thus, gate 502provides an output during the odd preparatory period when right-of-wayis on phase B1 and a call for right-of-Way has been received from phaseA1. This output from gate 502 passes through OR gate 504 to iire Schmitttrigger 506 which provides the signal AIPNFFSI that is applied to theset one input of PNFF 118 within the phase control unit associated withtraffic phase A1.

In like manner, AND gate S08 receives at its first input the signalB3PFF1 when the phase control unit associated with traic phase B3 iscontrolling the intersection. The A3PMFF1 signal is applied to thesecond input of gate 508 when a call for right-of-way has been receivedfrom traffic phase A3. When the odd interval sequence unit is in itsgreen preparatory position of counter position 6, the ISO(6) signal isapplied to the third input of gate 508. The output of gate 508 passesthrough OR gate 510 to re Schmitt trigger 512 which provides theA3PNFFS1 signal that sets PNFF 118 within the phase control unitassociated with trailic phase A3 to its one condition.

The output of gate 502 indicates that right-of-way is to transfer fromphase B1 to phase A1, both of which are non-conicting With phase A2.Similarly, the output of gate 508 indicates that right-of-way is totransfer' from phase B3 to phase A3, both of which are non-coniiictingwith phase A4. When such a transfer is made in the odd interval sequenceunit, no transfer is required on the even traic phases. Accordingly, theoutput of AND gate 502 and the output of AND gate 508 are passed throughOR gate 513, becoming the signal B/A call which is applied to the commonphase sequence unit circuitry of FIG. 8.

When the phase control unit associated with traffic phase A1 iscontrolling the intersection, the signal AlPP-'Fl is applied to the rstinput of AND gate 514. The ISO(6) signal is applied to the second inputof gate 514 during the preparatory interval of the odd interval sequenceunit. If there has not been a call for right-ofway from street II, thenthe signal -l- Ea is applied to the third input of gate 514. If the oddinterval sequence unit has been stepped to its preparatory positionWhile right-of-vvay is assigned to traiic phase A1 and there has notbeen a call for right-of-way from street II, then it must be requiredthat right-of-Way be transferred to phase B1. Accordingly the output ofgate 5'14 passes through OR gate 516 to tire Schmitt trigger 518,generating the signal B1PNFFS1 which is applied to set one input of PNFF118 within the phase control unit associated with traffic phase B1.

Similarly, the signal A3PFF1 is applied to the rst input of AND gate S20when phase control unit A3 is controlling the intersection. The ISO(6)signal is applied to the second input of gate 520 during the preparatoryinterval of the odd interval sequence unit. If there has not been a callfor rightof-way on street I, then the signal cl is applied to the thirdinput of gate 520. Accordingly, gate 520 provides an output when the oddinterval sequence unit is in its preparatory interval prepar ing totransfer right-of-way to another phase and when right-of-Way ispresently on phase A3, in the absence of a call from street I. Thiscondition means that right-of-way is next to be transferred to phase B3.Accordingly, the output of gate 520 passes through OR gate 522 to reSchmitt trigger 524, the output of which passes through OR gate 526 tobecome the signal B3PNFFS1 which is applied to the set one input of PNFF118 Within the phase control unit associated with traic phase B3. Thestart signal is also applied to the input of OR gate S26, so that, whenthe control system is first placed into operation, it commences with theintersection under the control of phase control unit B3.

AND gate 528 receives as its iirst input the signal AIPMFFI when a callhas been received for right-of-way on the trailic phase A1. The secondinput to AND gate 528 is the signal BIPMFFO which is present when therehas not-been a call for right-of-way on traflic phase B1. When thecommon portion of the phase control unit depicted in FIG. 8 indicatesthat right-of-Way is to be transferred from street Il to street I, aninput is applied to the third input of gate 528. On coincidence of thesethree inputs, gate 528 transmits a signal through OR gate 504 to iireSchmitt trigger S06, thereby generating the signal AIINFFSL The streetII to street I change signal is also applied as an input to AND gate 530which receives as its second input the signal B1PMFF1 when a call forright-of-way has been received from traffic phase B1` Coincidence ofthese two signals causes gate 530 to transmit a signal through OR gate516 to iire Schmitt trigger 518 generating the signal BlPNFFSl whichindicates that right-ofway is next to be assigned to phase B1. Thus,phase B1 is given priority over phase A1, and when a street II to streetI change is to be made, if a call for right-of-Way has been receivedfrom trafic phase B1, right-ofway is rst assigned to that phase, whethera call has been received from phase A1 or not. However, if no call hasbeen received from phase B1 but a call has been received forright-of-way from phase A1, then right-of-vvay is assigned to phase A1.

25 Similarly, AND gate 532 receives as its first input the signalA3PMFF1, as its second input the signal B3PMFFO and as its third inputthe street I to street II change signal provided by the common phasesequence unit circuitry of FIG. 8. On coincidence of these three signalsgate 532 passes a signal through OR gate 510 to fire Schmitt trigger512, thereby generating the signal A3PNFFS1 which indicates thatright-of-way is next to be assigned to phase A3. AND gate 534 receivesas its first input the street I to street II change signal and as itssecond input the signal B3PMFF1. Gate 534 passes its output through ORgate 522 to fire Schmitt trigger 524 which indicates that rightof-way isnext to be assigned to trafc phase B3. Hence, when the street I tostreet II change signal indicates that right-of-Way is to be transferredto street II, and a call for right-of-Way has been received from traicphase B3, that traic phase is next assigned right-of-Way, whether a callhas been received from phase A3 or not. But, in the absence of a callfor right-of-way from phase B3 and in the presence of a call forright-of-way from phase A3, then phase A3 is next assigned right-of-Way.

TRANSFER GATING CIRCUITRY-FIGURE Phase sequence unit 30 includes twosets of gating circuitry which generate the transfer commands for thetwo interval sequence units. FIG. 10 depicts the circuitry whichgenerates the signal ISO-TR to cause the odd interval sequence unit totransfer control of the intersection from one odd phase control unit toanother. A corresponding set of gating generates the transfer signalISE-TR for the even interval sequence unit.

OR gate 536 in FIG. 10 receives as inputs the signals AlPNFFl and B1PNFF1 when either Schmitt trigger 506 or Schmitt trigger 518 of FIG. 9 hascaused the phase next ip-flop PNFF 118 of phase A1 or PNFF 118 of phaseB1 respectively, either of which is illustrated in FIG. 4, to set to its1 condition. This output from gate 536 is applied as an input to ANDgate 538. Gate 538 also receives as inputs the signals A4PFFO and B4PFFOto indicate that the phase control units associated with traic phases A4and B4 are not controlling the intersection. In like manner the signalA3PNFF1 and the signal B3PNFF1 are applied as inputs to OR gate 540 whenthe phase next ip-flop in the phase control unit associated with eitherphase A3 or phase B3, respectively, is in its one condition. The outputof gate 540 is connected to one input of AND gate 542 which receives atits other inputs the signals A2PFFO and BZPFF() when phase control unitsA2 and B2 are not controlling the intersection. The outputs of the gates538 and 542 pass through OR gate 544 to one input of AND gate 546. Theother input of gate 546 is connected to the output of gate 72 associatedwith the counter of the odd interval sequence unit, shown in FIG. 3.This signal ISO(9) indicates that the counter Within the odd intervalsequence unit is in its transfer position 9.

The phase next flip-flop 11S (FIG. 4) within the phase control unit ofthe trac phase which is to be assigned right-of-Way is set to its onecondition during the preparatory interval of counter position 6. Duringthe transfer interval of counter position 9, the phase flip-flop 120within each phase control unit is setto its zero condition. Accordingly,during counter position 9, the signals AZPFFO, BZPFFQ, A4PFFO, andB4PFFO are all present. If for example, the right-of-way has been calledto phase A3, then the phase next flip-flop 118 within the phase controlunit associated with traffic phase A3 is set to its one condition, andso the signal A3PNFF1 passes through OR gate S40 (FIG. l0) to AND gate542. As a consequence, gate 542 passes its output through gate 544 toone input of AND gate 546. Thus, when the ISO(9) signal is applied togate 546, this gate generates the transfer signal for the odd intervalsequence unit, referred to as signal ISO-TR. This transfer signal isapplied to gates and 166 within the gating and timing circuitryassociated with the odd interval sequence unit, as shown in FIG. 5. As aconsequence, the odd interval sequence unit generates an advance pulseto step its counter to position 1, thereby initiating the control periodfor phase control unit A3. The even phase selection circuitry of thephase sequence unit 30 contains corresponding gates which undercorresponding conditions provide the ISE-TR signal which is applied tothe even interval sequence unit to step that counter from its transferposition 9 to its skip position 1.

If a call for single ended operation is received, only one transfersignal is generated. For example, if a call for even phase single endedoperation is received, no odd phase next tiip-op set one signal isgenerated. Accordingly, neither OR gate 536 nor OR gate 540 provides anoutput. Consequently, gate 546 cannot transmit the ISO- TR signal, andso the odd interval sequence unit rests in its counter position l9,causing red indications on all of its trafc phases, While the eveninterval sequence unit steps through its regular sequence. When thishappens the odd no call flip-flop ISONCFF, within the common circuitryof the phase sequence unit, is set to its one condition, providing thesignal ISONCFFl, as depicted in FIG. 8.

TRANSFER FROM SINGLE-ENDED TO DOUBLE- ENDED OPERATION ON THE SAMESTREET- FIGURE 9 When the tratiic control system is operating in evenphase single ended operation and a call for right-of-way is receivedfrom a non-conflicting traic phase on the same street, AND gate 54Sprovides a pulse which is passed through appropriate gating circuitry tore the appropriate Schmitt trigger 506, 512, 518, or 524 which generatesa signal to set the phase next iiip-op 118 in the phase control unit towhich right-of-way is to be called. The rst input to gate 548 is appliedfrom OR gate 550 which receives as inputs the signals from the memoryflip-flops of the odd trac phases. Thus the signals AlPMFFl, BlPMFFl,A3PMFF1, and B3PMFF1 are applied as inputs to gate 550, and whenever acall is present for right-of-way on one of the odd traflic phases, gateS50 applies an input to AND gate 548. The signal AZPFFI is applied as aninput to OR gate 552 which receives as its other input the signalB2PFF1. Thus whenever either phase control unit A2 or phase control unitB2 is controlling the intersection, a signal passes from OR gate 552 tothe first input of AND gate 554.

The signals A2PNFF1 and B2PNFF1 are provided as inputs to OR gate 556.The output of gate 556 is connected to the Second input of AND gate 554.Gate 554 has its output connected through OR gate 558 to one signalinput of INHIBITED-AND gate 560. The second signal input of gate 560receives the signal ISONCFFI during even phase single ended operation.The even interval sequence unit advance pulse is applied to the inhibitinput of gate 560 so that during this advance pulse gate S60 cannotpermit passage of its output signal.

INHIBITED-AND gate 562 receives the E green signal from inverter 76Within the even interval sequence unit. The inhibit input of gate 562receives the counter position 6 signal from gate 66 Within the eveninterval sequence unit. Therefore, gate 562 provides an output signalduring counter positions 1-5 of the even interval sequence unit. Thisoutput from gate 562 is connected as an input to OR gate 558.

In a similar manner, OR gate 564 receives as inputs the signals A4PFF1and B4PFF1 and applies its output to one input of AND gate 566. OR gate568 receives as inputs the signals A4PNFF1 and B4PNFF1 and provides itsoutput to the second input of gate 566. The output of gate 566 isconnected as an input of OR gate 558.

During even phase single ended operation, the signal ISONCFFI is appliedas an input to INHIBITED-AND

